Interleaving techniques for high-throughput chaotic noise generation in CMOS

TL;DR

This paper introduces an interleaving method to significantly increase the throughput of CMOS chaotic noise generators, preserving key statistical features and demonstrating application in high-speed communication systems.

Contribution

It presents a novel interleaving technique for CMOS chaotic sources that enhances throughput while maintaining statistical properties, with a practical circuit implementation at 20 Msample/s.

Findings

Achieved 20 Msample/s chaotic noise generation.

Preserved statistical features of chaotic signals.

Demonstrated application in FM-DCSK communication.

Abstract

An interleaving technique is proposed to enhance the throughput of current-mode CMOS discrete time chaotic sources based on the iteration of unidimensional maps. A discussion of the reasons and the advantages offered by the approach is provided, together with analytical results about the conservation of some major statistical features. As an example, application to an FM-DCSK communication system is proposed. To conclude, a sample circuit capable of 20 Msample/s is presented.