Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors

TL;DR

This paper presents architecture-aware optimizations for matrix multiplication on ARM big.LITTLE asymmetric multicore processors, improving performance and energy efficiency through cache-aware configuration and asymmetric scheduling strategies.

Contribution

It introduces a high-performance, energy-efficient GEMM implementation tailored for ARM big.LITTLE architectures using cache-aware and asymmetric scheduling techniques.

Findings

Significant performance improvements over architecture-oblivious implementations.

Enhanced energy efficiency on ARM big.LITTLE processors.

Effective utilization of heterogeneous cores for scientific computing.

Abstract

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications. In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication (gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric--static and dynamic scheduling strategies that carefully tune and distribute the operation's micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency.