Bilayer Insulator Tunnel Barriers for Graphene-Based Vertical Hot-electron Transistors

TL;DR

This paper demonstrates that bilayer insulator tunnel barriers significantly enhance electron injection in graphene-based vertical transistors, achieving high current densities and improved device performance suitable for future CMOS-compatible applications.

Contribution

It introduces a bilayer dielectric approach using TmSiO and TiO₂ to improve tunneling efficiency and device performance in graphene-based vertical transistors.

Findings

Achieved high tunneling current densities approaching 10^3 A/cm^2.

Demonstrated improved current-voltage nonlinearity and asymmetry.

Confirmed effectiveness in a full graphene-based transistor structure.

Abstract

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as the electron emitter in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transports. High injected tunneling current densities approaching 10$^3$ A/cm$^2$ (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm-thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO$_2$) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.