A Tailed Tent Map Chaotic Circuit Exploiting S$^2$I Memory Elements

TL;DR

This paper presents a chaotic circuit using a Tailed Tent Map and S$^2$I memory elements, achieving significantly faster operation through careful interfacing and simulation validation.

Contribution

It introduces a novel chaotic circuit design that integrates S$^2$I memory with the Tailed Tent Map, enabling improved speed and interface solutions.

Findings

Achieved fivefold speed improvement over previous designs.

Validated design effectiveness through SPICE simulations.

Demonstrated successful integration of memory and nonlinear chaotic elements.

Abstract

In the implementation of discrete time chaotic systems, designers have mostly focused on the choice and synthesis of suitable nonlinear blocks, while correct and fast operation cannot neglect analog memory elements. Herein, a realization exploiting the Tailed Tent Map coupled with S$^2$I sample and hold stages is proposed. Interfacing problems between the memory and the processing sub-circuits are tackled and the possibility to obtain a fivefold speed improvement with respect to previously reported results is demonstrated by means of SPICE and other computer aided simulations.