Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

TL;DR

This study investigates high-mobility InAs nanowire transistors, revealing transport mechanisms, defect effects, and providing a predictive modeling approach for device performance limits in next-generation nanoelectronics.

Contribution

It offers detailed analysis of carrier transport, defect impact, and a drift-diffusion simulation framework for InAs nanowire transistors, advancing understanding of their performance limits.

Findings

Carrier mobility reaches 2000 cm2/V.s at room temperature

Surface donors cause activated transport at low temperatures

Extended crystal defects reduce sound velocity in nanowires

Abstract

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.