4{\pi}{\beta} (LS)-{\gamma} (HPGe) Digital Coincidence System Based on Synchronous High-Speed Multichannel Data Acquisition

TL;DR

This paper presents a high-speed, synchronized digital coincidence system for 4πβ(LS)-γ(HPGe) detection, featuring multi-channel acquisition, high resolution, and a flexible, simplified structure suitable for various applications.

Contribution

The work introduces a novel multi-channel digital coincidence system with synchronized high-speed data acquisition for combined beta and gamma detection.

Findings

Achieved a maximum coincidence rate of 20K per second.

System synchronization within 500ps enhances detection accuracy.

Flexible design simplifies system structure and application.

Abstract

A dedicated 4{\pi}{\beta} (LS)-{\gamma} (HPGe)digital coincidence system has been developed in this work, which includes five acquisition channels. Three analog-to-digital converter (ADC) acquisition channels with an acquisition resolution of 8 bits and acquisition rate of 1GSPS (sample per second) are utilized to collect the signals from three Photo multiplier tubes (PMTs) which are adopted to detect {\beta} decay, and two acquisition channels with an acquisition resolution of 16 bits and acquisition rate of 50MSPS are utilized to collect the signals from high-purity germanium (HPGe) which are adopted to detect {\gamma} decay. In order to increase the accuracy of the coincidence system, all the five acquisition channels are synchronous within 500ps. The data collected by the five acquisition channels will be transmitted to the host PC through PCI bus and saved as a file. Off-line software is applied for the 4{\pi}{\beta} (LS)-{\gamma} (HPGe) coincidence and data analysis as needed in practical application. With all the above preconditions, the flexibility of the system is increased, and the structure and application of the system are simplified. According to the test, the highest coincidence rate of the system is 20K per second, which is sufficient for most applications. This paper mainly introduces the design of the hardware, the synchronization method and the test result of this system.