A hybrid partial sum computation unit architecture for list decoders of polar codes

TL;DR

This paper introduces a hybrid partial sum computation architecture for list decoders of polar codes, improving area efficiency through a lazy copy algorithm and combining registers and memory.

Contribution

It proposes a lazy copy partial sum algorithm and a hybrid architecture that enhances area efficiency in polar code list decoders.

Findings

Achieves 23% area saving for block length 2^{13} with list size 4.

Achieves 63% area saving for block length 2^{15} with list size 4.

Improves efficiency of partial sum updates in polar code list decoding.

Abstract

Although the successive cancelation (SC) algorithm works well for very long polar codes, its error performance for shorter polar codes is much worse. Several SC based list decoding algorithms have been proposed to improve the error performances of both long and short polar codes. A significant step of SC based list decoding algorithms is the updating of partial sums for all decoding paths. In this paper, we first proposed a lazy copy partial sum computation algorithm for SC based list decoding algorithms. Instead of copying partial sums directly, our lazy copy algorithm copies indices of partial sums. Based on our lazy copy algorithm, we propose a hybrid partial sum computation unit architecture, which employs both registers and memories so that the overall area efficiency is improved. Compared with a recent partial sum computation unit for list decoders, when the list size $L=4$, our partial sum computation unit achieves an area saving of 23\% and 63\% for block length $2^{13}$ and $2^{15}$, respectively.