Formally Proved Security of Assembly Code Against Power Analysis: A Case Study on Balanced Logic

TL;DR

This paper introduces formal methods and tools for designing and verifying assembly code protected against power analysis attacks, demonstrated through a case study on an 8-bit AVR smartcard achieving significant resistance improvements.

Contribution

It presents a novel approach to automatically insert and verify power balancing countermeasures at the assembly level, bridging the gap between models and implementations.

Findings

Automated assembly-level insertion of power balancing measures

Proven security of the generated code against power analysis

Achieved at least 250 times increased resistance to CPA attacks

Abstract

In his keynote speech at CHES 2004, Kocher advocated that side-channel attacks were an illustration that formal cryptography was not as secure as it was believed because some assumptions (e.g., no auxiliary information is available during the computation) were not modeled. This failure is caused by formal methods' focus on models rather than implementations. In this paper we present formal methods and tools for designing protected code and proving its security against power analysis. These formal methods avoid the discrepancy between the model and the implementation by working on the latter rather than on a high-level model. Indeed, our methods allow us (a) to automatically insert a power balancing countermeasure directly at the assembly level, and to prove the correctness of the induced code transformation; and (b) to prove that the obtained code is balanced with regard to a reasonable leakage model. We also show how to characterize the hardware to use the resources which maximize the relevancy of the model. The tools implementing our methods are then demonstrated in a case study on an 8-bit AVR smartcard for which we generate a provably protected present implementation that reveals to be at least 250 times more resistant to CPA attacks.