Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems

TL;DR

This paper introduces a novel technique that significantly speeds up the exploration of non-volatile and hybrid processor cache designs for embedded systems, using new modeling and prediction methods to optimize performance.

Contribution

It presents a new cache behavior model and miss prediction mechanism that greatly accelerates cache design space exploration for application-specific embedded systems.

Findings

Achieves up to 249x speedup in cache design exploration

Effective modeling of cache behavior for NVM and hybrid caches

Accurate cache miss prediction mechanism

Abstract

In this article, we propose a technique to accelerate nonvolatile or hybrid of volatile and nonvolatile processor cache design space exploration for application specific embedded systems. Utilizing a novel cache behavior modeling equation and a new accurate cache miss prediction mechanism, our proposed technique can accelerate NVM or hybrid FIFO processor cache design space exploration for SPEC CPU 2000 applications up to 249 times compared to the conventional approach.