TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs

TL;DR

TRISHUL is a novel trace-driven method that rapidly predicts and identifies the optimal two-level inclusive data cache hierarchy for real-time MPSoCs, significantly reducing size and improving speed over existing approaches.

Contribution

It introduces the first fast, accurate trace-driven approach for optimal cache hierarchy selection tailored to real-time applications in MPSoCs.

Findings

Up to 128 times smaller cache size

Up to 7 times faster cache hierarchy selection

More accurate than crude estimation methods

Abstract

Hitherto discovered approaches analyze the execution time of a real time application on all the possible cache hierarchy setups to find the application specific optimal two level inclusive data cache hierarchy to reduce cost, space and energy consumption while satisfying the time deadline in real time Multiprocessor Systems on Chip. These brute force like approaches can take years to complete. Alternatively, memory access trace driven crude estimation methods can find a cache hierarchy quickly by compromising the accuracy of results. In this article, for the first time, we propose a fast and accurate trace driven approach to find the optimal real time application specific two level inclusive data cache hierarchy. Our proposed approach TRISHUL predicts the optimal cache hierarchy performance first and then utilizes that information to find the optimal cache hierarchy quickly. TRISHUL can suggest a cache hierarchy, which has up to 128 times smaller size, up to 7 times faster compared to the suggestion of the state of the art crude trace driven two level inclusive cache hierarchy selection approach for the application traces analyzed.