Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric

TL;DR

This paper presents Skybridge, a novel nanoscale 3D integrated circuit fabric that addresses CMOS scaling challenges through a new manufacturing pathway involving uniform vertical nanowires and sequential material deposition.

Contribution

It introduces a comprehensive manufacturing process for Skybridge, enabling fine-grained 3D integration with experimental validation of key steps.

Findings

Skybridge achieves nanoscale integration benefits over CMOS.

Experimental demonstrations validate the manufacturing process steps.

The process reduces lithography and doping precision requirements.

Abstract

At sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3D has been long sought as a possible pathway to continue scaling, however, intrinsic requirements of CMOS are not compatible for fine-grained 3D integration. We proposed a truly fine-grained 3D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3D compatible manner. At the core of Skybridge assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping are performed prior to any functionalization and their precision requirements are significantly reduced. This paper introduces Skybridge manufacturing pathway that is developed based on extensive process, device simulations and experimental metrology, and uses established processes. Experimental demonstrations of key process steps are also shown.