The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities

TL;DR

This paper presents a fully-synchronous multi-GHz analog waveform recorder chip with Nyquist-rate sampling, high trigger bandwidth, and stable timing, suitable for high-speed signal acquisition in a compact CMOS package.

Contribution

The SST recorder introduces a fully-synchronous digital design enabling multi-GHz sampling with ps-level timing stability and flexible trigger capabilities in a low-cost CMOS implementation.

Findings

Achieves over 1.5 GHz bandwidth with 12+ bits dynamic range.

Operates at 2 G-samples/sec with ~128 mW power consumption.

Provides stable timing over a wide frequency range from 2 kHz to 2 GHz.

Abstract

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with intrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth, wide dynamic range and simple operation. Containing 4 channels of 256 samples per channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOS process and uses a high-performance package that is 8 mm on a side. It has a 1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses ~128 mW while operating at 2 G-samples/s and full trigger rates. With a standard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator running at half the sample rate (e.g., a 1 GHz oscillator yields 2 G-samples/s). Because of its purely-digital synchronous nature, the SST has ps-level timing uniformity that is independent of sample frequencies spanning over 6 orders of magnitude: from under 2 kHz to over 2 GHz. Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. When operating as common-stop device, the time of the stop, modulo 256 relative to the start, is read out along with the sampled signal values. Each of the four channels integrates dual-threshold trigger circuitry with windowed coincidence features. Channels can discriminate signals with ~1mV RMS resolution at >600 MHz bandwidth.