A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R

TL;DR

This paper presents a high-speed, 2.48Gb/s QC-LDPC decoder implemented on a single FPGA for 5G wireless systems, demonstrating rapid development and scalability using LabVIEW CSDS tools.

Contribution

The paper introduces the fastest known QC-LDPC decoder implementation on a USRP platform using an algorithmic compiler, highlighting rapid prototyping and scalability.

Findings

Achieved 2.48Gb/s decoding speed at 200MHz on FPGA

Used LabVIEW CSDS for rapid HDL generation in 2 minutes

Demonstrated scalability and high throughput for 5G applications

Abstract

The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding subsystems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present a massively-parallel 2.48Gb/s Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder implementation operating at 200MHz on the NI USRP-2953R, on a single FPGA. The high-level description of the entire massively-parallel decoder was translated to a Hardware Description Language (HDL), namely VHDL, using the algorithmic compiler in the National Instruments LabVIEW Communication System Design Suite (CSDS) in approximately 2 minutes. This implementation not only demonstrates the scalability of our decoder architecture but also, the rapid prototyping capability of the LabVIEW CSDS tools. As per our knowledge, at the time of writing this paper, this is the fastest implementation of a standard compliant QC-LDPC decoder on a USRP using an algorithmic compiler.