Hold-in, pull-in, and lock-in ranges of PLL circuits: rigorous mathematical definitions and limitations of classical theory

TL;DR

This paper provides rigorous mathematical definitions for PLL hold-in, pull-in, and lock-in ranges, clarifying ambiguities in classical engineering concepts and proposing solutions for their precise characterization.

Contribution

It introduces mathematically rigorous definitions for PLL frequency ranges and addresses the ambiguity in the classical concept of lock-in frequency.

Findings

Hold-in and pull-in ranges may be unions of intervals, not simple intervals.

A rigorous mathematical framework for PLL ranges is established.

A solution for the unique definition of lock-in frequency is proposed.

Abstract

The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions are given for these concepts in engineering literature. After many years of their usage, F.~Gardner in the 2nd edition of his well-known work, Phaselock Techniques, wrote "There is no natural way to define exactly any unique lock-in frequency" and "despite its vague reality, lock-in range is a useful concept." Recently these observations have led to the following advice given in a handbook on synchronization and communications "We recommend that you check these definitions carefully before using them." In this survey it is shown that, from a mathematical point of view, in some cases the hold-in and pull-in "ranges" may not be the intervals of values but a union of intervals and thus their widely used definitions require clarification. Rigorous mathematical definitions for the hold-in, pull-in, and lock-in ranges are given. An effective solution for the problem on the unique definition of the lock-in frequency, posed by Gardner, is suggested.