Computationally efficient formulation of relay operator for Preisach hysteresis modeling

TL;DR

This paper introduces a new algebraic expression for the Preisach hysteron, enabling efficient real-time computation and parallel implementation on hardware like FPGA or ASIC, facilitating practical applications.

Contribution

It presents a novel algebraic formulation of the Preisach hysteron that significantly improves computational efficiency for real-time hardware implementation.

Findings

The algebraic expression allows parallel computation of hysterons.

Hardware implementation on FPGA/ASIC demonstrates real-time performance.

Numerical and real-time tests validate the approach.

Abstract

An algebraic expression for the Preisach hysteron, which is a non-ideal (delayed) relay operator, is formulated for a computationally efficient real-time implementation. This allows representing the classical scalar Preisach hysteresis model as a summation of a large number of weighted hysterons which computation can be accomplished in parallel. The latter makes possible an efficient FPGA or ASIC realization of the scalar Preisach hysteresis model that can be useful for multiple applications. The signal flow which specifies the model implementation is provided in form of the block diagram. The proposed computation of Preisach hysterons, aggregated to the entire Preisach hysteresis model, is evaluated numerically and on a real-time hardware platform.