FPGA-Based Bandwidth Selection for Kernel Density Estimation Using High Level Synthesis Approach

TL;DR

This paper presents an FPGA implementation of a bandwidth selection algorithm for kernel density estimation using High Level Synthesis, demonstrating significant speedups and lower power consumption compared to CPU and GPU solutions.

Contribution

The paper introduces an FPGA-based implementation of KDE bandwidth selection via HLS, optimizing the process and comparing its performance and power efficiency with CPU and GPU methods.

Findings

FPGA implementation achieves substantial speedups over CPU and GPU.

Power consumption of FPGA is significantly lower than CPUs and GPUs.

Optimizations in HLS improve FPGA performance for KDE tasks.

Abstract

FPGA technology can offer significantly hi\-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using ha\-rdware description languages, HDL) is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty the High Level Synthesis (HLS) approach is promoting by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.