InAs nanowire transistors with multiple, independent wrap-gate segments

TL;DR

This paper introduces a scalable fabrication method for horizontal InAs nanowire transistors with up to four independent wrap-gate segments, enabling advanced device architectures with minimal cross-talk and high integration potential.

Contribution

It presents a fabrication approach that allows multiple independent wrap-gate segments on horizontal nanowires without extra steps beyond two gates, unlike vertical designs.

Findings

Negligible cross-talk between adjacent gates at <200 nm separation

Successful fabrication of multiple transistors on a single nanowire

Scalable process suitable for complex 3D nanowire networks

Abstract

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favourable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.