Transistor Switches using Active Piezoelectric Gate Barriers

TL;DR

This paper investigates how integrating a piezoelectric gate barrier into transistors can enhance performance by amplifying internal charge and potentially reducing subthreshold slope below thermal limits, with implications for hysteresis.

Contribution

It introduces a novel transistor design with a piezoelectric gate barrier that enables negative capacitance and improved switching characteristics.

Findings

Internal charge amplification due to piezoelectric feedback

Potential to reduce subthreshold slope below 60 mV/decade

Hysteretic behavior may occur in transfer characteristics

Abstract

This work explores the consequences of introducing a piezoelectric gate barrier in a normal field-effect transistor. Because of the positive feedback of strain and piezoelectric charge, internal charge amplification occurs in such an electromechanical capacitor resulting in a negative capacitance. The first consequence of this amplification is a boost in the on-current of the transistor. As a second consequence, employing the Lagrangian method, we find that by using the negative capacitance of a highly compliant piezoelectric barrier, one can potentially reduce the subthreshold slope of a transistor below the room temperature Boltzmann limit of 60 mV/decade. However, this may come at the cost of hysteretic behavior in the transfer characteristics.