TC: Throughput Centric Successive Cancellation Decoder Hardware Implementation for Polar Codes

TL;DR

This paper introduces a hardware architecture for fast-SSC polar code decoding that reduces latency and increases throughput, compatible with any rate, and demonstrates significant performance improvements over existing decoders.

Contribution

The paper presents a rate-compatible hardware design for fast-SSC polar code decoding that achieves substantial latency reduction and high throughput using a unified architecture.

Findings

At least 60% latency reduction for length 1024 codes.

Throughput up to 5.81 Gbps for (1024, 870) polar code.

Throughput up to 2.01 Gbps for (1024, 512) polar code.

Abstract

This paper presents a hardware architecture of fast simplified successive cancellation (fast-SSC) algorithm for polar codes, which significantly reduces the decoding latency and dramatically increases the throughput. Algorithmically, fast-SSC algorithm suffers from the fact that its decoder scheduling and the consequent architecture depends on the code rate; this is a challenge for rate-compatible system. However, by exploiting the homogeneousness between the decoding processes of fast constituent polar codes and regular polar codes, the presented design is compatible with any rate. The scheduling plan and the intendedly designed process core are also described. Results show that, compared with the state-of-art decoder, proposed design can achieve at least 60% latency reduction for the codes with length N = 1024. By using Nangate FreePDK 45nm process, proposed design can reach throughput up to 5.81 Gbps and 2.01 Gbps for (1024, 870) and (1024, 512) polar code, respectively.