An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs

TL;DR

This paper introduces TyTra-IR, an intermediate language for FPGA design space exploration, along with a cost model for resource and throughput estimation, demonstrated through a kernel example.

Contribution

The work presents a novel intermediate language and a cost model tailored for FPGA design space exploration and automated estimation.

Findings

TyTra-IR effectively expresses multiple FPGA configurations.

The cost model accurately estimates resource usage and throughput.

Demonstration with SOR kernel validates the approach.

Abstract

We present the TyTra-IR, a new intermediate language intended as a compilation target for high-level language compilers and a front-end for HDL code generators. We develop the requirements of this new language based on the design-space of FPGAs that it should be able to express and the estimation-space in which each configuration from the design-space should be mappable in an automated design flow. We use a simple kernel to illustrate multiple configurations using the semantics of TyTra-IR. The key novelty of this work is the cost model for resource-costs and throughput for different configurations of interest for a particular kernel. Through the realistic example of a Successive Over-Relaxation kernel implemented both in TyTra-IR and HDL, we demonstrate both the expressiveness of the IR and the accuracy of our cost model.