Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics

TL;DR

This paper assesses whether ARM's asymmetric big.LITTLE multicore architecture can serve as an energy-efficient alternative to traditional high-performance processors in unreliable, low-power computing scenarios, using the Conjugate Gradient algorithm as a case study.

Contribution

It introduces an evaluation framework for asymmetric multicore SoCs under power constraints and unreliability, focusing on energy efficiency and performance trade-offs.

Findings

Asymmetric big.LITTLE architecture reduces power consumption significantly.

Performance degradation is manageable with error-tolerant algorithms.

Energy efficiency improves compared to conventional multicore processors.

Abstract

The end of Dennard scaling has pushed power consumption into a first order concern for current systems, on par with performance. As a result, near-threshold voltage computing (NTVC) has been proposed as a potential means to tackle the limited cooling capacity of CMOS technology. Hardware operating in NTV consumes significantly less power, at the cost of lower frequency, and thus reduced performance, as well as increased error rates. In this paper, we investigate if a low-power systems-on-chip, consisting of ARM's asymmetric big.LITTLE technology, can be an alternative to conventional high performance multicore processors in terms of power/energy in an unreliable scenario. For our study, we use the Conjugate Gradient solver, an algorithm representative of the computations performed by a large range of scientific and engineering codes.