A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization

TL;DR

This paper develops a detailed compact model for CNT-based FETs, incorporating parasitic effects and tunneling currents, to optimize device parameters for sub-10nm technology nodes and project future performance.

Contribution

It introduces a data-calibrated compact model including extrinsic effects and performs a co-optimization study for CNFETs near the scaling limits.

Findings

A CNT density of 180 CNTs/μm meets ITRS drive current targets.

The model predicts CNFET performance at the 5-nm node with a 31 nm gate pitch.

Including parasitic effects is crucial for accurate device performance assessment.

Abstract

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/{\mu}m will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/{\mu}m), which is within reach of modern experimental capabilities