Inhomogeneity in barrier height at graphene/Si (GaAs) Schottky junctions

TL;DR

This study investigates the inhomogeneity of Schottky barrier heights at graphene/Si and graphene/GaAs junctions, revealing temperature-dependent variations and interfacial states that affect device performance.

Contribution

It provides the first detailed analysis of barrier inhomogeneities in graphene/semiconductor Schottky junctions using temperature-dependent measurements and microscopy.

Findings

Barrier height increases with temperature.

Ideality factor decreases with temperature.

Barrier inhomogeneities are linked to interfacial states.

Abstract

Graphene interfaced with a semiconductor forms a Schottky junction with rectifying properties, however, fluctuations in the Schottky barrier height are often observed. In this work, Schottky junctions are fabricated by transferring chemical vapor deposited monolayer graphene onto n-type Si and GaAs substrates. Temperature dependence of the barrier height and ideality factor are obtained by current-voltage measurements between 215 and 350 K. An increase in the zero bias barrier height and decrease in the ideality factor are observed with increasing temperature for both junctions. Such behavior is attributed to barrier inhomogeneities that arise from interfacial states as revealed by scanning tunneling microscopy/spectroscopy. Assuming a Gaussian distribution of the barrier heights, mean values of 1.14(+/-)0.14 eV and 0.76(+/-)0.10 eV are found for graphene Si and GaAs junctions, respectively. These findings provide insights into the barrier height inhomogeneities in graphene based Schottky junctions, essential for the integration of graphene with Si and GaAs device architectures.