Design of High Performance MIPS Cryptography Processor Based on T-DES Algorithm

TL;DR

This paper presents a high-performance MIPS cryptography processor integrated with T-DES encryption, featuring pipeline optimization, new instructions, and synthesis on 40nm technology achieving 209MHz operation.

Contribution

It introduces a novel MIPS processor design with T-DES encryption and three new instructions, enhancing security and performance for cryptographic applications.

Findings

Processor operates at 209MHz

Includes three new instructions for security functions

Synthesized on 40nm Xilinx Virtex-6 platform

Abstract

The paper describes the design of high performance MIPS Cryptography processor based on triple data encryption standard. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of triple data encryption standard (T-DES) crypto system and dependency among themselves are explained in detail with the help of block diagram. In order to increase the processor functionality and performance, especially for security applications we include three new 32-bit instructions LKLW, LKUW and CRYPT. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The overall MIPS Crypto processor works at 209MHz.