Clock Auto-synchronizing Method for BES III ETOF Upgrade

TL;DR

This paper presents an FPGA-based automatic clock synchronization method for BESIII ETOF upgrade, achieving low jitter and automatic synchronization, simplifying system setup and maintenance.

Contribution

It introduces a novel FPGA-based automatic clock synchronization technique for BESIII ETOF, enhancing precision and operational efficiency.

Findings

Achieved clock jitter less than 20ps RMS.

Successfully demonstrated automatic synchronization to beam bunches.

System has passed multiple successful tests.

Abstract

An automatic clock synchronizing method implemented in field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing Spectrometer (BESIII). In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from external clock synchronization circuit. By testing different delay time of the detection signal and analyzing state signals returned, the synchronization windows will be found automatically in FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square (RMS), but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.