Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

TL;DR

This paper details the design and testing of a custom ASIC digitizer in 65 nm CMOS technology for wire chamber readout, achieving high timing resolution and good linearity with low power consumption.

Contribution

It introduces a novel 4-channel ASIC prototype integrating TDCs, ADC, and buffers for wire chamber readout in 65 nm CMOS technology.

Findings

TDC resolution ranges from 74 ps to 480 ps

Relative time resolution of 19 ps achieved

ADC exhibits an effective number of bits of 6.9

Abstract

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.