Hardware Architecture for Single Iteration Reconstruction Algorithm

TL;DR

This paper presents a hardware architecture for a single iteration signal reconstruction algorithm that efficiently reconstructs signals from limited samples, suitable for FPGA implementation and capable of distinguishing signal from noise.

Contribution

The paper introduces a novel FPGA-compatible hardware architecture for the single iteration reconstruction algorithm, including custom blocks for non-standard components.

Findings

Efficient FPGA implementation of the reconstruction algorithm.

Capability to distinguish signal components from noise.

Design of custom FPGA blocks for non-standard functions.

Abstract

A hardware architecture for the single iteration algorithm is proposed in this paper. Single iteration algorithm enables reconstruction of the full signal when small number of signal samples is available. The algorithm is based on the threshold calculation, and allows distinguishing between signal components and noise that appears as a consequence of missing samples. The proposed system for hardware realization is divided into three parts, each part with different functionality. The system is suitable for the FPGA realization. Realization of the blocks for which there are no standard components in FPGA, is discussed as well.