A Flexible Implementation of a Matrix Laurent Series-Based 16-Point Fast Fourier and Hartley Transforms

TL;DR

This paper introduces a flexible hardware architecture for fast 16-point Fourier and Hartley transforms using a matrix Laurent series, achieving high-speed computation on FPGA with a single bit selection operator.

Contribution

It presents a novel hardware implementation of Fourier and Hartley transforms based on matrix Laurent series, optimized for FPGA with high speed and flexibility.

Findings

Achieved 65 ns computation time for 16-point transforms.

Implemented on Xilinx SPARTAN 3E FPGA device.

Demonstrated flexibility in transform computation.

Abstract

This paper describes a flexible architecture for implementing a new fast computation of the discrete Fourier and Hartley transforms, which is based on a matrix Laurent series. The device calculates the transforms based on a single bit selection operator. The hardware structure and synthesis are presented, which handled a 16-point fast transform in 65 nsec, with a Xilinx SPARTAN 3E device.