Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

TL;DR

This paper introduces a novel electrostatically doped planar FET compatible with CMOS technology, demonstrating high-temperature robustness through dual-gate control and Schottky barrier engineering, supported by experimental and simulation data.

Contribution

It presents a new voltage-programmable, electrostatically doped planar FET with dual-gate architecture based on Si-nanowire technology, enhancing high-temperature performance.

Findings

Demonstrated high-temperature operation stability.

Achieved voltage programmability via electrostatic doping.

Validated device performance through experiments and simulations.

Abstract

In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establish Schottky barrier FET (SBFET) operation and one front-gate forming a junctionless FET (JLFET) for actual current control, significantly increases the temperature robustness of the device.