A High-Performance Solid-State Disk with Double-Data-Rate NAND Flash Memory

TL;DR

This paper introduces a SSD architecture using double-data-rate NAND flash that doubles data transfer speed without extra pins, significantly enhancing read/write performance and energy efficiency across different NAND flash types.

Contribution

The paper presents a novel SSD design with a double-data-rate interface that improves performance while maintaining backward compatibility.

Findings

Read speeds increased by up to 2.76 times

Write speeds increased by up to 2.45 times

Energy consumption was reduced with the new architecture

Abstract

We propose a novel solid-state disk (SSD) architecture that utilizes a double-data-rate synchronous NAND flash interface for improving read and write performance. Unlike the conventional design, the data transfer rate in the proposed design is doubled in harmony with synchronous signaling. The new architecture does not require any extra pins with respect to the conventional architecture, thereby guaranteeing backward compatibility. For performance evaluation, we simulated various SSD designs that adopt the proposed architecture and measured their performance in terms of read/write bandwidths and energy consumption. Both NAND flash cell types, namely single-level cells (SLCs) and multi-level cells (MLCs), were considered. In the experiments using SLC-type NAND flash chips, the read and write speeds of the proposed architecture were 1.65-2.76 times and 1.09-2.45 times faster than those of the conventional architecture, respectively. Similar improvements were observed for the MLC-based architectures tested. It was particularly effective to combine the proposed architecture with the way-interleaving technique that multiplexes the data channel between the controller and each flash chip. For a reasonably high degree of way interleaving, the read/write performance and the energy consumption of our approach were notably better than those of the conventional design.