A high precision TDC based on a multi-phase clock

TL;DR

This paper presents a high-precision TDC using multiphase clocks on an FPGA, achieving 1/8 clock period resolution with good linearity and stability, suitable for accurate time interval measurements.

Contribution

The paper introduces a novel FPGA-based TDC design utilizing four multiphase clocks for enhanced resolution and a discriminator circuit for uncertain start/stop signals, improving measurement accuracy.

Findings

Achieves 1/8 of a clock period resolution.

Maintains high linearity and stability.

Consumes fewer logic resources.

Abstract

The design of a high-precision time-to-digital converter (TDC) based on a multiphase clock implemented using a single field-programmable gate array is discussed in this paper. The TDC can increase the resolution of the measurement by using time interpolation. A phase-locked loop is used to generate four multiphase clocks whose frequencies are the same and whose phases are 0{\deg}, 45{\deg}, 90{\deg}, and 135{\deg}. In addition, the duty ratios of the four clocks are 50%. By utilizing four multiphase clocks to make up the interpolation clock, one clock period can be divided into eight uniform parts. The resolution of the TDC can be improved to 1/8 of a clock period. Furthermore, we have also designed a discriminator circuit for identifying the start and stop signals. On the basis of this circuit, the TDC can still measure the time interval of two signals when the start and stop signals are uncertain. The experimental results indicate that the time resolution of the TDC can achieve the theoretical value, and the linearity is very good. The architecture consumes fewer logic cells and is more stable.