Hall and field-effect mobilities in few layered $p$-WSe$_2$ field-effect transistors

TL;DR

This study compares temperature-dependent field-effect and Hall mobilities in few-layer WSe$_2$ transistors, revealing high mobilities and disorder effects, and suggests fabrication improvements for enhanced device performance.

Contribution

It provides the first detailed comparison of field-effect and Hall mobilities in few-layer WSe$_2$ and highlights the impact of interface disorder on carrier transport.

Findings

Maximum room temperature hole mobility ~350 cm$^2$/Vs

Hall mobility exceeds 650 cm$^2$/Vs below 150 K

Disorder-induced carrier localization observed

Abstract

Here, we present a temperature ($T$) dependent comparison between field-effect and Hall mobilities in field-effect transistors based on few-layered WSe$_2$ exfoliated onto SiO$_2$. Without dielectric engineering and beyond a $T$-dependent threshold gate-voltage, we observe maximum hole mobilities approaching 350 cm$^2$/Vs at $T$=300 K. The hole Hall mobility reaches a maximum value of 650 cm$^2$/Vs as $T$ is lowered below $\sim$ 150 K, indicating that insofar WSe$_2$-based field-effect transistors (FETs) display the largest Hall mobilities among the transition metal dichalcogenides. The gate capacitance, as extracted from the Hall-effect, reveals the presence of spurious charges in the channel, while the two-terminal sheet resistivity displays two-dimensional variable-range hopping behavior, indicating carrier localization induced by disorder at the interface between WSe$_2$ and SiO$_2$. We argue that improvements in the fabrication protocols as, for example, the use of a substrate free of dangling bonds are likely to produce WSe$_2$-based FETs displaying higher room temperature mobilities, i.e. approaching those of $p$-doped Si, which would make it a suitable candidate for high performance opto-electronics.