Tejas Simulator : Validation against Hardware
Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep, Goel
TL;DR
This paper validates the Tejas architectural simulator by comparing its performance predictions against native hardware, showing competitive error rates on standard benchmarks.
Contribution
It provides a validation of the Tejas simulator with error metrics that are comparable or better than existing simulators.
Findings
Mean error rate of 11.45% on SPEC2006
Mean error rate of 18.77% on Splash2
Performance predictions are competitive with other simulators
Abstract
In this report we show results that validate the Tejas architectural simulator against native hardware. We report mean error rates of 11.45% and 18.77% for the SPEC2006 and Splash2 benchmark suites respectively. These error rates are competitive and in most cases better than the numbers reported by other contemporary simulators.
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Distributed and Parallel Computing Systems · Embedded Systems Design Techniques