A Customized Lattice Reduction Multiprocessor for MIMO Detection

TL;DR

This paper introduces a specialized multiprocessor architecture based on TTA cores for efficient lattice reduction in MIMO detection, significantly improving throughput and performance in signal processing tasks.

Contribution

It presents a novel homogeneous multiprocessor design with modified LLL algorithm and high-level language programmability for enhanced MIMO detection performance.

Findings

Achieves 187 cycles for lattice reduction of a matrix.

Synthesized on 90 nm technology with 405,000 gates at 210 MHz.

Provides high throughput for MIMO detection applications.

Abstract

Lattice reduction (LR) is a preprocessing technique for multiple-input multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER) performance. In this paper, we propose a customized homogeneous multiprocessor for LR. The processor cores are based on transport triggered architecture (TTA). We propose some modification of the popular LR algorithm, Lenstra-Lenstra-Lovasz (LLL) for high throughput. The TTA cores are programmed with high level language. Each TTA core consists of several special function units to accelerate the program code. The multiprocessor takes 187 cycles to reduce a single matrix for LR. The architecture is synthesized on 90 nm technology and takes 405 kgates at 210 MHz.