Symbol-Decision Successive Cancellation List Decoder for Polar Codes

TL;DR

This paper introduces symbol-decision successive cancellation and list decoders for polar codes, improving throughput and error performance through recursive channel combination, a two-stage list pruning network, and memory-saving techniques, with efficient hardware architecture.

Contribution

It proposes a novel symbol-wise decoding approach for polar codes, including recursive channel combination, a two-stage list pruning, and memory optimization, enhancing hardware efficiency and performance.

Findings

Symbol-decision decoders outperform bit-decision decoders in area efficiency.

Recursive channel combination reduces complexity compared to bit-wise methods.

Hardware architecture achieves higher throughput with various symbol sizes.

Abstract

Polar codes are of great interests because they provably achieve the capacity of both discrete and continuous memoryless channels while having an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. In this paper, we propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. First, we propose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination also has a lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arikan's channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. Second, a two-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Third, since memory is a significant part of SCL decoders, we propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder. Finally, to evaluate the throughput advantage of our symbol-decision decoders, we design an architecture based on a semi-parallel successive cancellation list decoder. In this architecture, different symbol sizes, sorting implementations, and message scheduling schemes are considered. Our synthesis results show that in terms of area efficiency, our symbol-decision SCL decoders outperform both bit- and symbol-decision SCL decoders.