Two-Level Rectilinear Steiner Trees
Stephan Held, Nicolas K\"ammerling

TL;DR
This paper introduces algorithms for constructing two-level rectilinear Steiner trees that optimize total length, including a PTAS for bounded cases and a practical 2.37-approximation for general cases, relevant in chip design.
Contribution
It presents a polynomial time approximation scheme for bounded cases and a fast 2.37-approximation algorithm for the general two-level rectilinear Steiner tree problem.
Findings
PTAS based on Arora's method for bounded k
A 2.37-approximation algorithm for general cases
Reduction of approximation factor to 1.63 with Arora's scheme
Abstract
Given a set of terminals in the plane and a partition of into subsets , a two-level rectilinear Steiner tree consists of a rectilinear Steiner tree connecting the terminals in each set () and a top-level tree connecting the trees . The goal is to minimize the total length of all trees. This problem arises naturally in the design of low-power physical implementations of parity functions on a computer chip. For bounded we present a polynomial time approximation scheme (PTAS) that is based on Arora's PTAS for rectilinear Steiner trees after lifting each partition into an extra dimension. For the general case we propose an algorithm that predetermines a connection point for each and (). Then, we apply any approximation algorithm for minimum rectilinear Steiner trees in the plane to…
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Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · VLSI and Analog Circuit Testing
