A new algorithm for multiplying two Dirac numbers

TL;DR

This paper introduces a low-complexity, FPGA-friendly algorithm for multiplying Dirac numbers, significantly reducing the number of real multiplications compared to the naive approach.

Contribution

A novel rationalized algorithm for Dirac numbers multiplication that exploits matrix structure to minimize computational complexity.

Findings

Reduces real multiplications from 256 to 88

Maintains similar addition count as naive method

Suitable for FPGA implementation

Abstract

In this work a rationalized algorithm for Dirac numbers multiplication is presented. This algorithm has a low computational complexity feature and is well suited to FPGA implementation. The computation of two Dirac numbers product using the na\"ive method takes 256 real multiplications and 240 real additions, while the proposed algorithm can compute the same result in only 88 real multiplications and 256 real additions. During synthesis of the discussed algorithm we use the fact that Dirac numbers product may be represented as vector-matrix product. The matrix participating in the product has unique structural properties that allow performing its advantageous decomposition. Namely this decomposition leads to significant reducing of the computational complexity.