Silicon MOS Pixel Based on the Deep Trapping Gate Principle: Design and Material Science Challenges
Nicolas T. Fourches (CEA-Saclay/IRFU/SEDI/DePhys), G. Regula, W., Vervisch (Aix-Marseille University)

TL;DR
This paper explores the design, simulation, and fabrication challenges of a deep trapping gate (DTG) silicon MOS pixel, proposing potential techniques like impurity implantation and quantum dots, and assessing their feasibility for advanced pixel detectors.
Contribution
It introduces the concept of a DTG pixel device, evaluates its physical operation through simulations, and discusses various fabrication techniques and their potential challenges.
Findings
Simulations show sufficient signal for energy deposition by minimum ionizing particles.
All studied fabrication techniques are potentially feasible with manageable challenges.
Deep level concentrations in DTG exceed radiation-induced defect levels for certain fluences.
Abstract
The deep trapping gate pixel device was described recently as an alternative to CMOS 3T pixel. The feasibilty of this device was studied with technological and transport simulations used in classical electron devices and process design. A buried gate containing localized deep level centers (Deep Trapping Gate or DTG) is the key for the operation of this field effect pixel detector. This can be made with deep levels or a quantum box. This buried gate can modulates the drain-source current, the same way the upper gate does. This principle was evaluated with realistic simulations physical parameters and this shows that the signal magnitude is sufficient for an energy deposition of a Minimum Ionizing Particle within a limited silicon thickness (a few microns). We will study here the potential techniques usable for the fabrication of the device with their drawbacks, advantages and limits.…
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Taxonomy
TopicsSemiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis
