Computationally Efficient Implementation of a Hamming Code Decoder using a Graphics Processing Unit

TL;DR

This paper introduces an optimized GPU implementation of a Hamming code decoder that significantly accelerates decoding for real-time wireless communication, overcoming parallelization challenges inherent in the algorithm.

Contribution

The paper presents a novel GPU-based implementation of the Hamming code decoder that addresses parallelization challenges and achieves high speedup over CPU implementations.

Findings

Achieved 99x speedup compared to CPU implementation.

Effectively handled data sparsity and thread divergence issues.

Demonstrated suitability for real-time software-defined radio applications.

Abstract

This paper presents a computationally efficient implementation of a Hamming code decoder on a graphics processing unit (GPU) to support real-time software-defined radio (SDR), which is a software alternative for realizing wireless communication. The Hamming code algorithm is challenging to parallelize effectively on a GPU because it works on sparsely located data items with several conditional statements, leading to non-coalesced, long latency, global memory access, and huge thread divergence. To address these issues, we propose an optimized implementation of the Hamming code on the GPU to exploit the higher parallelism inherent in the algorithm. Experimental results using a compute unified device architecture (CUDA)-enabled NVIDIA GeForce GTX 560, including 335 cores, revealed that the proposed approach achieved a 99x speedup versus the equivalent CPU-based implementation.