TL;DR
The paper discusses the planned upgrade of the LHCb detector, focusing on new hardware components, data handling, and performance simulations to enhance experimental capabilities.
Contribution
It presents the design and expected performance of the upgraded detector components, including the hybrid pixel vertex detector and data acquisition system.
Findings
Design specifications for the new detector components
Projected data rates and transmission capabilities
Simulated performance metrics of the upgraded detector
Abstract
A significant upgrade of the LHCb detector is scheduled to be installed in 2018-2019. Afterwards all sub-detectors will be read out at the LHC bunch crossing frequency of 40 MHz and the trigger will be fully implemented in software. The silicon strip vertex detector will be replaced by a hybrid pixel detector. In these proceedings the following items are discussed: frontend ASIC, data rates, data transmission, cooling, radiation hard sensors, module design and simulated performance.
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