A 237 Gbps Unrolled Hardware Polar Decoder

TL;DR

This paper introduces a fully-unrolled, deeply-pipelined FPGA architecture for polar decoding that achieves over 237 Gbps throughput, significantly surpassing existing decoders in speed.

Contribution

The paper presents a novel hardware architecture for polar decoders that dramatically increases decoding speed using unrolled and pipelined design techniques.

Findings

Achieves 237 Gbps throughput on FPGA

Two orders of magnitude faster than previous decoders

Uses reduced complexity successive cancellation algorithm

Abstract

In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.