Energy Consumption of VLSI Decoders
Christopher Blake, Frank R. Kschischang

TL;DR
This paper establishes fundamental lower bounds on the energy required for VLSI decoding circuits, showing that energy per bit must grow with block length, especially as codes approach capacity, and analyzes different computation models.
Contribution
It introduces new theoretical lower bounds on decoding energy in VLSI circuits, extending Thompson's model to serial and variable-output scenarios.
Findings
Energy per bit scales at least as Omega((log n)^(1/2)) for large block lengths.
Serial computation requires energy scaling as Omega(n log n).
Energy complexity for certain circuits can be as high as O(n^2 log log n).
Abstract
Thompson's model of VLSI computation relates the energy of a computation to the product of the circuit area and the number of clock cycles needed to carry out the computation. It is shown that for any family of circuits implemented according to this model, using any algorithm that performs decoding of a codeword passed through a binary erasure channel, as the block length approaches infinity either (a) the probability of block error is asymptotically lower bounded by 1/2 or (b) the energy of the computation scales at least as Omega(n(log n)^(1/2)), and so the energy of successful decoding, per decoded bit, must scale at least as Omega((log n)^(1/2)). This implies that the average energy per decoded bit must approach infinity for any sequence of codes that approaches capacity. The analysis techniques used are then extended to the case of serial computation, showing that if a circuit is…
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Taxonomy
TopicsLow-power high-performance VLSI design · Error Correcting Code Techniques · Coding theory and cryptography
