Complexity issues in some clustering problems in combinatorial circuits
Zola Donovan, Vahan Mkrtchyan, K. Subramani

TL;DR
This paper investigates the computational complexity of clustering problems in combinatorial circuit design, demonstrating NP-hardness and approximability limits for certain delay minimization problems without logic replication.
Contribution
It establishes NP-hardness and approximation bounds for specific clustering problems in combinatorial circuits, highlighting their computational difficulty.
Findings
Selected clustering variants are NP-hard.
Approximation and inapproximability results are provided.
Delay minimization problems without logic replication are computationally challenging.
Abstract
The modern integrated circuit is one of the most complex products that has been engineered to-date. It continues to grow in complexity as the years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface \cite{Lim08}. The process of mapping an electronic design to a chip involves a number of physical design stages, one of which is clustering. In this paper, we focus on problems in clustering which are critical for more sustainable chips. The clustering problem in combinatorial circuits alone is a source of multiple models. In particular, we consider the…
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Taxonomy
TopicsComplexity and Algorithms in Graphs · Interconnection Networks and Systems · Advanced Graph Theory Research
