Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS

TL;DR

This paper presents a 28 nm CMOS neuromorphic system using switched-capacitor circuits to implement synaptic plasticity and stop-learning mechanisms, achieving real-time operation with scalable, technology-portable design.

Contribution

It introduces a novel switched-capacitor based approach for synaptic dynamics in advanced CMOS technology, overcoming limitations of analog subthreshold circuits.

Findings

128 short-term plasticity presynapses implemented

8192 stop-learning synapses realized

System consumes 1.9 mW in 0.36 mm2 area

Abstract

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the mil- lisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromor- phic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to sev- eral seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.