Sphynx: A Shared Instruction Cache Exporatory Study

TL;DR

This paper explores a shared instruction cache approach for massively parallel multi-core processors to reduce instruction replication overhead and save die area, especially as core counts increase.

Contribution

It proposes a technique for sharing instruction caches among multiple cores to enable inter-thread instruction sharing and reuse.

Findings

Reduces instruction cache duplication in many-core systems.

Potential to decrease die area for instruction storage.

Highlights importance of shared caches as core counts grow.

Abstract

The Sphynx project was an exploratory study to discover what might be done to improve the heavy replication of in- structions in independent instruction caches for a massively parallel machine where a single program is executing across all of the cores. While a machine with only many cores (fewer than 50) might not have any issues replicating the instructions for each core, as we approach the era where thousands of cores can be placed on one chip, the overhead of instruction replication may become unacceptably large. We believe that a large amount of sharing should be possible when the ma- chine is configured for all of the threads to issue from the same set of instructions. We propose a technique that allows sharing an instruction cache among a number of independent processor cores to allow for inter-thread sharing and reuse of instruction memory. While we do not have test cases to demonstrate the potential magnitude of performance gains that could be achieved, the potential for sharing reduces the die area required for instruction storage on chip.