Dynamic Verification of SystemC with Statistical Model Checking
Van Chan Ngo (ESPRESSO), Axel Legay (ESTASYS), Jean Quilbeuf (ESTASYS)

TL;DR
This paper introduces a framework for verifying probabilistic and temporal properties of large embedded systems modeled in SystemC using Statistical Model Checking, overcoming state space explosion issues.
Contribution
It presents a novel verification framework based on Statistical Model Checking for SystemC models, extending Plasma-lab to handle large probabilistic systems.
Findings
Successfully verified a multi-lift system case study.
Demonstrated scalability on large SystemC models.
Provided probabilistic guarantees for system properties.
Abstract
Many embedded and real-time systems have a inherent probabilistic behaviour (sensors data, unreliable hardware,...). In that context, it is crucial to evaluate system properties such as "the probability that a particular hardware fails". Such properties can be evaluated by using probabilistic model checking. However, this technique fails on models representing realistic embedded and real-time systems because of the state space explosion. To overcome this problem, we propose a verification framework based on Statistical Model Checking. Our framework is able to evaluate probabilistic and temporal properties on large systems modelled in SystemC, a standard system-level modelling language. It is fully implemented as an extension of the Plasma-lab statistical model checker. We illustrate our approach on a multi-lift system case study.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Formal Methods in Verification · Embedded Systems Design Techniques
