Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

TL;DR

This paper presents memristive-CMOS threshold logic circuits for efficient FFT and Vedic multiplication, demonstrating improved performance metrics over previous designs, with potential for brain-inspired computing architectures.

Contribution

It introduces advanced memristive threshold logic gates integrated with CMOS for complex computing tasks like FFT and multiplication.

Findings

Lower chip area compared to previous designs

Reduced total harmonic distortion (THD)

Controllable leakage power with higher power dissipation

Abstract

Brain inspired circuits can provide an alternative solution to implement computing architectures taking advantage of fault tolerance and generalisation ability of logic gates. In this brief, we advance over the memristive threshold circuit configuration consisting of memristive averaging circuit in combination with operational amplifier and/or CMOS inverters in application to realizing complex computing circuits. The developed memristive threshold logic gates are used for designing FFT and multiplication circuits useful for modern microprocessors. Overall, the proposed threshold logic outperforms previous memristive-CMOS logic cells on every aspect, however, indicate a lower chip area, lower THD, and controllable leakage power, but a higher power dissipation with respect to CMOS logic.