Sub 20 nm Silicon Patterning and Metal Lift-Off Using Thermal Scanning Probe Lithography

TL;DR

This paper demonstrates that thermal scanning probe lithography can create sub 20 nm dense silicon and metal patterns with high precision, enabling advanced nanoscale device fabrication.

Contribution

It introduces a novel process combining t-SPL with a multi-layer stack for sub 20 nm patterning and metal lift-off, achieving high resolution and low edge roughness.

Findings

Sub 20 nm patterning in silicon and metals achieved

Line edge roughness less than 3 nm

Successful fabrication of 50 nm nickel contacts on nanowires

Abstract

The most direct definition of a patterning process' resolution is the smallest half-pitch feature it is capable of transferring onto the substrate. Here we demonstrate that thermal Scanning Probe Lithography (t-SPL) is capable of fabricating dense line patterns in silicon and metal lift-off features at sub 20 nm feature size. The dense silicon lines were written at a half pitch of 18.3 nm to a depth of 5 nm into a 9 nm polyphthalaldehyde thermal imaging layer by t-SPL. For processing we used a three-layer stack comprising an evaporated SiO2 hardmask which is just 2-3 nm thick. The hardmask is used to amplify the pattern into a 50 nm thick polymeric transfer layer. The transfer layer subsequently serves as an etch mask for transfer into silicon to a nominal depth of 60 nm. The line edge roughness (3 sigma) was evaluated to be less than 3 nm both in the transfer layer and in silicon. We also demonstrate that a similar three-layer stack can be used for metal lift-off of high resolution patterns. A device application is demonstrated by fabricating 50 nm half pitch dense nickel contacts to an InAs nanowire.