High Performance Field-Effect Transistor Based on Multilayer Tungsten Disulfide

TL;DR

This paper demonstrates a high-performance multilayer tungsten disulfide transistor with an on/off ratio of 10^8 and mobility of 234 cm^2V^-1s^-1, achieved through optimized contact and thickness, highlighting its potential for future electronics.

Contribution

It introduces a simple fabrication method for high-performance tungsten disulfide transistors using gold contacts and specific thickness control, with detailed analysis of the underlying mechanisms.

Findings

Achieved high on/off ratio of 10^8 and mobility of 234 cm^2V^-1s^-1 at room temperature.

Identified minimized Schottky barrier and shallow impurity levels as key factors.

Suppressed phonon scattering and low impurity density contribute to high mobility.

Abstract

Semiconducting two-dimensional transition metal chalcogenide crystals have been regarded as the promising candidate for the future generation of transistor in modern electronics. However, how to fabricate those crystals into practical devices with acceptable performance still remains as a challenge. Employing tungsten disulfide multilayer thin crystals, we demonstrate that using gold as the only contact metal and choosing appropriate thickness of the crystal, high performance transistor with on/off ratio of $10^{8}$ and mobility up to $234\:cm^{2}V^{-1}s^{-1}$ at room temperature can be realized in a simple device structure. Further low temperature study revealed that the high performance of our device is caused by the minimized Schottky barrier at the contact and the existence of a shallow impurity level around 80 meV right below the conduction band edge. From the analysis on temperature dependence of field-effect mobility, we conclude that strongly suppressed phonon scattering and relatively low charge impurity density are the key factors leading to the high mobility of our tungsten disulfide devices.