Cycle slipping in nonlinear circuits under periodic nonlinearities and time delays
Vera Smirnova, Anton Proskurnikov, and Natalia V. Utina

TL;DR
This paper provides analytical estimates for cycle slipping in nonlinear PLL-based circuits with delays, capturing complex dynamics and the effects of small perturbations, which are crucial for reliable telecommunications.
Contribution
It introduces a novel analytical approach to estimate cycle slipping in systems with delays and high-order dynamics, extending prior stochastic-focused results.
Findings
Derived bounds for the number of cycle slips in delayed systems
Analyzed the impact of small parameter perturbations on cycle slipping
Captured effects of high-order dynamics and delays on phase error behavior
Abstract
Phase-locked loops (PLL), Costas loops and other synchronizing circuits are featured by the presence of a nonlinear phase detector, described by a periodic nonlinearity. In general, nonlinearities can cause complex behavior of the system such multi-stability and chaos. However, even phase locking may be guaranteed under any initial conditions, the transient behavior of the circuit can be unsatisfactory due to the cycle slipping. Growth of the phase error caused by cycle slipping is undesirable, leading e.g. to demodulation and decoding errors. This makes the problem of estimating the phase error oscillations and number of slipped cycles in nonlinear PLL-based circuits extremely important for modern telecommunications. Most mathematical results in this direction, available in the literature, examine the probability density of the phase error and expected number of slipped cycles under…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
